International Conference «Mathematical and Informational Technologies, MIT-2013»
(X Conference «Computational and Informational Technologies for Science,
Engineering and Education»)

Vrnjacka Banja, Serbia, September, 5–8, 2013

Budva, Montenegro, September, 9-14, 2013

Stamenkovic N.   Zivaljevic D.   Stojanovic V.  

Diminished-One Modulo (2n+1) Multiplier Design

Reporter: Stamenkovic N.

A technique based on the residue number system has been used in several applications that include digital signal processing (DSP), implementation in international data encryption algorithm (IDEA), in the Fermat number transform (FNT), and so on. Diminishedone modulo (2n + 1) multiplication plays an important role in these techniques. For the implementation of these techniques several designs for diminished-one modulo 2n + 1 arithmetic blocks have been proposed. Existing algorithms for modulo diminished-one (2n + 1) multiplication either use recursive modulo (2n + 1) addition, or a regular binary multiplication integrated with the modulo reduction operation. A new method for designing modulo (2n + 1) multipliers for diminished-one operands is proposed i this paper. The architecture for the new multipliers consists of a new partial product generator, an inverted end-around-carry save adder Wallace tree and one modulo (2n+1) adder. This architecture exhibits an extremely modular structure with associated
VLSI implementation advantages. The critical path delay and the hardware requirements of the new multiplier are similar to that of a corresponding n × n bit binary multiplier.

Full text file: Stamenkovic N.pdf

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